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> verilator
verilator
Verilator is the fastest free Verilog HDL simulator. It compiles synthesizable SystemVerilog into multi-threaded C++ or SystemC code.
Current version
:
5.014
History
Effective Date
Table ID
Version
Download URL
Project URL
Version URL
2024-08-26
12
5.014
download
project
version
2022-03-31
11
4.108
download
project
version